	中国嵌入式创新应用大会
	首届中国开源IP核标准化设计竞赛结果评选结果揭晓
	数字软 IP 核质量标准自评表格（简化版）
	Innovision公司与全球领先的半导体公司签定NFC合约
	Beceem选用CEVA-XC DSP内核-Beceem采用CEVA旗舰产品CEVA-XC DSP内核

	MediaLB Device Interface [ 2010.08.31 ]
	CAN Module [ 2010.08.31 ]
	Advanced CAN Module [ 2010.08.31 ]
	LGMAC [ 2010.08.31 ]
	Gigabit Ethernet MAC [ 2010.08.31 ]
	Gigabit Ethernet MAC [ 2010.08.31 ]
	USB Highspeed Device [ 2010.08.31 ]
	USB2_OTG - USB Highspeed OTG for Nios®II [ 2010.08.31 ]
	IEEE 1588 [ 2010.08.31 ]
	CDSP - General purpose, high performance customizable fixed-point DSP core [ 2010.08.31 ]
	AST DES Core - Data Encryption Standard (DES) Core [ 2010.08.31 ]
	M8051EW [ 2010.08.23 ]
	M8051W [ 2010.08.23 ]
	M8052 [ 2010.08.23 ]
	M8051 [ 2010.08.23 ]
	ESSHCH1601是一种采用迭代结构设计的，用可综合的Verilog HDL语言风格进行设计的基于CORDIC算法的实现计算双曲正弦余弦Sinh Cosh功能的IP软核。 [ 2010.08.17 ]
	ESDES01是一种采用迭代结构设计的，用可综合的Verilog HDL语言风格进行设计的实现Data Encryption Standard (DES)加解密算法标准的IP软核。 [ 2010.08.17 ]
	ES3DES02是一种采用流水线结构，用可综合的Verilog HDL语言风格进行设计的实现Triple Data Encryption Standard (3DES)加解密算法标准的IP软核。 [ 2010.08.17 ]
	ES3DES01是一种采用迭代结构设计，用可综合的Verilog HDL语言风格进行设计的实现Triple Data Encryption Standard (3DES)加解密算法标准的IP软核。 [ 2010.08.17 ]
	ESDES02是一种采用流水线结构设计的，用可综合的Verilog HDL语言风格进行设计的实现Data Encryption Standard (DES)加解密算法标准的IP软核。 [ 2010.08.17 ]

	RISC Secure RISC Core C310
	Secure RISC Core CS320
	32 bits RISC CPU Core with CACHE andMMU
	Optimally Performance/Power/Memory balanced DSP core
	XtensaⅤ是可配置的处理器
	Very low power, compact DSP Core
	Haokai_PLL_130CHRT_02, a 0.13 μm phase locked loop ;Output frequency range: 20 MHz to 1.0 GHz,RMS period jitter: 3.5 ps
	SMIC 0.18um 3.3v-1.8v Power Regulator
	a complete, silicon-proven, system-level IP interface operating at up to 1600 Mbps.
	Optimized for low area and power DDR2/3-Lite SDRAM IP complete solution.
	Mid-range DSP core
	Licensable, High-Performance Application Oriented DSP Processor
	Floating Point Multiplier - (Module Compiler Only)
	Haokai_PLL_130SMIC_02, a 0.13 μm phase locked loop;Output frequency range: 20 MHz to 1.4 GHz,RMS period jitter: 4 ps
	High Speed SPI - AHB IP Core
	Optimized for low area and power DDR2/3-Lite SDRAM IP complete solution.
	Arithmetic Saturation and Rounding Logic
	J83 A,B,C and DVB-C channel decoder
	STM0/1/4 SDH Deframer Core
	Secure RISC Core CS320D

	JPEG 2000 压缩IP [ 2010.08.05 ]
	10位30M ADC 硬核 [ 2010.08.03 ]
	FFT [ 2010.07.08 ]
	实现turbo码 IP [ 2010.05.13 ]
	标准8051软核采购-电科院 [ 2010.05.09 ]
	spi [ 2010.04.11 ]
	数字上下变频 [ 2010.03.29 ]
	数字上下变频 [ 2010.03.29 ]
	low power IP core optimizition [ 2010.03.04 ]
	AVR8位IP核 [ 2010.03.03 ]
	需求80251 IP核 [ 2009.08.31 ]
	8051 IP Core [ 2009.07.13 ]
	flash EEPROM [ 2008.10.31 ]
	8通道单端/差分16位A/D模数转换器 IP Core [ 2008.09.11 ]
	EEPROM或Flash IP Core [ 2008.09.11 ]
	C8051 IP Core [ 2008.09.11 ]
	DRAM [ 2008.08.12 ]
	i2c_master [ 2008.08.10 ]

	The Universal Serial Bus (USB) has evolved to the standard interconnect between computers and peripherals.
	Core_arm
	MC8051. Oregano Systems 8-bit Microcontroller IP-Core
	I2C
	I2C-Master / Slave Core
	PCI_core
	Ethernet
	SDRAM
	jpeg
	FFTProcessor
	RISCMCU
	Synthesizable model of Atmel ATmega103 microcontroller
	microprocessor
	Bluetooth
	can
	AHBAHB
	Embedded_risc
	camera
	PS2
	SARM7TM

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